1. Field
The invention relates to a field of digital circuitry, and more particularly to digital latching circuits.
2. Background Information
One conventional circuit to latch signals is called the flip-flop. A so-called xe2x80x9cDxe2x80x9d style flip-flop, well known in the art, may be implemented using a pair of latch circuits known as a master-slave latch pair. The master-slave latch pair may be arranged in a cascade configuration, such that the data output terminal Q of the master latch is coupled to the data input terminal D of the slave latch. The master latch may receive a data signal on a master data input D and, upon receiving a latch signal, propagate the data signal to master data output terminal Q. The latch signal may be received on a master latch terminal C. The data signal may be propagated to the master output terminal Q when the latch signal achieves a first predetermined voltage level. This first predetermined voltage level may correspond to logical xe2x80x9chighxe2x80x9d or logical xe2x80x9clowxe2x80x9d in binary signal systems. The slave latch receives the data signal at slave data input terminal D. The slave latch propagates the data signal to a slave output terminal Q upon receiving an inverted latch signal at slave latch terminal C. The inverted latch signal received by the slave latch may be an inverted form of the latch signal received by the master latch.
In other words, the data signal at the input terminal of the master latch (this may also act as the input terminal of the flip-flop) is xe2x80x9clatchedxe2x80x9d, e.g. stored to the output terminal of the master latch when the latch signal achieves a first predetermined voltage level. The data signal is propagated to the output terminal of the slave latch (which may also act as the output terminal of the flip-flop) when the latch signal (which is inverted when received by the slave latch) achieves a second predetermined voltage level (the inverted level of the first predetermined voltage level).
One problem with conventional flip-flops is that the latch signal may arrive before the data signal has become stable at the data input terminal. Once the data signal arrives at the data terminal, an amount of time called the setup time must typically elapse before the master latch is capable of latching the data signal. This amount of time is known as the setup time for the flip-flop. If the clock signals arrives before the setup time has elapsed the flip-flop may not function as intended. In particular, the flip-flop may latch a signal which is not an accurate representation of the data signal.
One approach to this problem is to delay the latch signal so that it arrives at the latch terminals later. This gives the data signal more time to settle at the data input terminal of the flip-flop. A disadvantage of this approach is that the output signal of the flip-flop is delayed by an amount of time which may be directly proportional to the amount of time which the latch signal is delayed. The longer the latch signal is delayed the longer the output of the flip-flop is delayed. If other circuits depend upon receiving the output of the flip-flop, operation of those circuits may also be delayed by a corresponding amount of time.
There exists a continuing need for a technique by which the latching of the data signal may be delayed by an interval of time without delaying the output signal of the flip-flop by a proportional interval of time.
According to an embodiment of the invention, An apparatus includes a first latch having an output terminal. A latch signal is received by the first latch. A second receives the latch signal and has an input terminal coupled to the output terminal of the first latch. A delay circuit delays the latch signal to the first latch. An inverter inverts the latch signal to the first latch. Other embodiments are also described and claimed.